Clocked Comparator

For a course in Full Custom Integrated Circuit Design, I researched the design of clocked comparators in CMOS technology. The comparator takes a differential analogue input and produces a digital output that results from the comparison of the inputs. The design focused on achieving the highest possible clock frequency, without intolerable trade-off of other values of merit, such as input referred offset voltage.

A final design was produced in Cadence Virtuoso and simulated.

Design achievements:

• 6GHz maximum clock frequency
• 60ps Clk to Q delay
• 1.5mW power dissipation
• 128 square micrometer layout

Knowledge gained:

• VLSS literature review technique
• Candence Virtuoso design and simulation
• Non-idealities of mixed signal CMOS design

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